A flash or block erase memory (flash memory), for example, Electrically Erasable Programmable Read-Only Memory (Flash EEPROM), includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide Semiconductor (MOS) memory cells that are field effect transistors (FETs). Each FET, or flash memory cell includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. Programming occurs by hot electron injection in order to program the floating gate. Erasure employs Fowler-Nordheim tunneling effects in which electrons punch through a thin dielectric layer, thereby reducing the amount of charge on the floating gate. Erasing a cell sets the logical value of the cell to “1,” while programming a cell sets the logical value to “0.” The flash memory cell provides for nonvolatile data storage.
Prior Art FIG. 1 illustrates a typical configuration of a plan view of a section of a memory array 100 in a NOR-type of configuration for a memory device. Prior Art FIG. 1 is not drawn to scale. As shown in Prior Art FIG. 1, the array 100 is comprised of rows 10 and columns 120 of memory cells. Each of the memory cells are isolated from other memory cells by insulating layers (e.g., a plurality of shallow trench isolation regions (STI) 150).
The control gates of each of the memory cells are coupled together in each of the plurality of rows 110 of memory cells, and form a plurality of word lines 130 that extend along the row direction.
Bit lines extend in the column direction and are coupled to drain regions via drain contacts 168 in an associated column of memory cells 120. The bit lines are coupled to drain regions of memory cells in associated columns of memory cells 120.
A plurality of source lines 140 extend in the row direction and are coupled to the source regions of each of the memory cells in the array of memory cells 100. One source line is coupled to source regions in adjoining rows of memory cells, and as a result, one source region is shared between two memory cells. Similarly, drain regions are shared amongst adjoining rows of memory cells, and as a result, one drain region is shared between two memory cells.
A plurality of source contacts are coupled to the plurality of common source lines 140. Each of the plurality of source contacts 145 is formed in line with the associated common source line to which it is coupled. The source contacts are formed in a column 160, and may be coupled with each other. The column 160 is isolated between two STI regions and forms a dead zone in which no memory cells are present.
The well known Moore's Law of the semiconductor field states that the number of semiconductor devices, e.g., transistors, per unit area will double every 18-24 months. While other factors such as design improvements contribute, one of the fundamental drivers of this inexorable density increase is the ever shrinking minimum feature size of semiconductors. For example, a common minimum feature size of modern semiconductors is 0.11 microns.
As shown in FIG. 1, due to current photolithography limitations in forming contact vias, each of the plurality of source contacts 145 is larger than their associated common source lines 140. As a result, the common source lines 140 need to be widened in the region surrounding their associated source contacts 145. This is to accommodate the wider source contacts 145. As such, word lines one either side of the common source line 140 are bent to accommodate for the increased area for the common source line surrounding an associated source contact 145.
However, as the size of each memory cell and correspondingly, the array 100 itself is reduced, the bending of the word lines to accommodate for the size of the source contacts is limited by current photolithography and chemical vaporization deposition (CVD) techniques. For example, as the size shrinks, it becomes more difficult to form a pronounced bend in each of the plurality of word lines 130 at current pitches achievable by current photolithography techniques. As a result, the size of the overall array 100 is limited by the ability to bend the word lines 130.
Furthermore, the inability to form straight word lines in the region surrounding the source contacts 145 effects the uniformity of cells throughout the array 100. More specifically, the memory cells bordering the column of source contacts 160 that includes the source contacts 145 may have electrical characteristics (erase and program) that are different from those of memory cells that do not border a column of source contacts. Voltage thresholds and current leakage are specific problems. In particular, a change in the erasing characteristics of a memory cell bordering the column of source contacts 160 can alter the threshold voltage of the cell into the negative region. This causes cell current to always flow (leakage) irrespective of the associated word line potential. As such, memory cells lying on the same bit line as the defective cell will have an erroneous state being read.
Semiconductor processing equipment is extremely expensive. Fundamental semiconductor processing steps, e.g., implantation, diffusion and etching, typically require long periods of development and extensive qualification testing. Implementing a new fabrication process requires considerable resources on the part of the semiconductor manufacturer. A manufacturer may have to alter or entirely revamp process libraries and process flows in order to implement a new fabrication process. Additionally, re-tooling a fabrication line is very expensive, both in terms of direct expenses as well as in terms of opportunity cost due to the time required to perform the re-tooling. Consequently, any solution to standing waves within photoresist should be compatible with existing semiconductor processes and equipment without the need for revamping well established tools and techniques.
Accordingly, a need exists for a semiconductor memory device with better uniformity and performance uniformity between memory cells in an array of memory cells, thus leading to better fabrication yields. A further need exists for an array of memory cells that is more compact by extending beyond the size limitations due to source contact formation. An even further need exists for a word line formation that can accommodate the decreasing size of the array of memory cells using current photolithography techniques.